The subject invention relates generally to a paged memory management unit (PMMU) for use in a data processing system, and, more particularly, to a PMMU which supports access protection to portions of a logical address space.
In some data processing systems, a paged memory management unit (PMMU) is used to translate a logical portion of an address provided by a processor to a memory via an address bus into a corresponding portion of a physical address. Often, associated with the PMMU is a translation cache comprising a plurality of storage locations for storing recently used translators. In response to each logical address provided by the processor, the PMMU searches the translation cache for a corresponding logical-to-physical translator. If none is found, the processor is directed to abort the access cycle and release the system bus so that the PMMU can access a set of translation tables stored in the memory to determine the proper logical-to-physical address translator to enter in the translation cache. Subsequently, when the processor restarts the aborted access cycle, the PMMU will use the new translator in the translation cache to determine the proper physical address to forward to the memory. Thereafter, whenever the processor again accesses a logical address in the same logical page, the PMMU will reuse the translator in the translation cache.
In simple virtual memory systems, there is only a single "privilege level", that of the program currently executing in the processor. Since the PMMU has access to only a single set of translation tables, the same access privileges are applied to all accesses made by that program. In some applications, however, it is desirable to provide different privileges to certain broad classes of accesses which might be made by that program.
In some virtual memory systems, a plurality of separate and distinct "address spaces" are provided and assigned as needed to particular programs. For example, in U.S. Pat. No. 4,430,705, the processor provides an "Address Space Number" together with each logical address so that the PMMU can access the particular set of translation tables appropriate for the program assigned that address space. (See, also, U.S. Pat. Nos. 4,057,848, 4,068,303, 4,145,738, and 4,326,248.) Thus, different access privileges can be applied to each different address space as appropriate. On the other hand, since each program is typically assigned only a single address space, there is still no way to apply different access privileges to independent routines or "modules" within a given program.
In other virtual memory systems, not only are different access privileges assigned to the supervisor and user programs, but separate privileges may also be provided for the instructions and the data of each of these categories of programs. For example, in the data processing system described in U.S. Pat. Nos. 4,084,225, 4,084,226, and 4,084,227, the processor provides a "task name" together with each logical address to advise the PMMU which address space to use to translate that logical address. In U.S. Pat. No. 4,241,401, this system is expanded to provide for a plurality of "interrupt levels" and the PMMU is enabled to distinguish between multiple executions of the same task at different interrupt levels to assure that a task executing at one interrupt level cannot use the translators of the same task executing at a different interrupt level. However, while these systems allow code and data of a given program to have different access privileges, none allow different portions of the code or data spaces to have different access privileges.
In U.S. Pat. No. 4,434,464, code and data areas of memory are protected using unique "memory protection" keys which are maintained in the processor. If access to an area having a more restrictive key is required, a special instruction may be executed to temporarily alter the protection key of the executing program. In general, it appears feasible to include such access protection information in the cache of a virtual memory system. However, in addition to significantly expanding the width of the cache, the time and hardware required to perform access protection verification on a cycle-by-cycle basis is quite significant.